HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 219

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
2.2.57 (6)
SHAL (L)
SHAL (SHift Arithmetic Left)
Operation
ERd (left arithmetic shift)
ERd
Assembly-Language Format
SHAL.L #2, ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) two bits to the left.
Bit 30 shifts into the carry flag. Bits 0 and 1 are cleared to 0.
C
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Addressing
Mnemonic
Mode
Register direct
SHAL.L
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Condition Code
I
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
cleared to 0.
Z: Set to 1 if the result is zero; otherwise
cleared to 0.
V: Set to 1 if an overflow occurs; otherwise
cleared to 0.
C: Receives the previous value in bit 30.
MSB
. . . . . .
b31
b30
Instruction Format
Operands
1st byte
2nd byte
#2, ERd
1
0
F
0 erd
Rev. 4.00 Feb 24, 2006 page 203 of 322
Section 2 Instruction Descriptions
Shift Arithmetic
UI H
U
N
Z
V
C
LSB
0
0
0
b1
b0
No. of
States
3rd byte
4th byte
REJ09B0139-0400
1

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