HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 231

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
2.2.59 (6)
SHLL (SHift Logical Left)
Operation
ERd (left logical shift)
Assembly-Language Format
SHLL.L #2, ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) two bits to the left.
Bit 30 shifts into the carry flag. Bits 0 and 1 are cleared to 0.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.
Register direct
Addressing
Mode
SHLL (L)
Mnemonic
SHLL.L
C
ERd
MSB
Operands
b31
#2, ERd
b30
1st byte
1
. . . .
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 30.
2nd byte
7
Instruction Format
cleared to 0.
cleared to 0.
Rev. 4.00 Feb 24, 2006 page 215 of 322
I
0 erd
UI H
b1
0
Section 2 Instruction Descriptions
3rd byte
LSB
b0
0
U
N
0
4th byte
REJ09B0139-0400
Z
Shift Logical
V
0
States
No. of
C
1

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