HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 26

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

13.2 LBSC Operation................................................................................................................ 376
Section 14 Direct Memory Access Controller (DMAC)
14.1 Overview........................................................................................................................... 379
14.2 Register Descriptions ........................................................................................................ 384
14.3 Operation........................................................................................................................... 398
14.4 Compare-Match Timer (CMT) ......................................................................................... 431
14.5 Examples for Use .............................................................................................................. 438
14.6 Usage Notes ...................................................................................................................... 441
Rev.6.00 Mar. 27, 2009 Page xxiv of lvi
REJ09B0254-0600
13.2.1 Bus Sharing Architecture ..................................................................................... 376
13.2.2 Usable System Memory ....................................................................................... 376
13.2.3 Bus Arbitration .................................................................................................... 376
13.2.4 LCDC Li Bus Access........................................................................................... 376
13.2.5 USBH Li Bus Access........................................................................................... 377
13.2.6 Setting of DMA Transfer with Bus Arbitration of Other Module........................ 377
14.1.1 Features................................................................................................................ 379
14.1.2 Block Diagram..................................................................................................... 381
14.1.3 Pin Configuration................................................................................................. 382
14.1.4 Register Configuration......................................................................................... 382
14.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3) .................................... 384
14.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)............................ 385
14.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3) .................. 386
14.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3)............................. 387
14.2.5 DMA Channel Request Assign Register (CHRAR) ............................................ 394
14.2.6 DMA Operation Register (DMAOR)................................................................... 396
14.3.1 DMA Transfer Flow ............................................................................................ 398
14.3.2 DMA Transfer Requests ...................................................................................... 400
14.3.3 Channel Priority ................................................................................................... 402
14.3.4 DMA Transfer Types........................................................................................... 405
14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 418
14.3.6 Source Address Reload Function......................................................................... 427
14.3.7 DMA Transfer Ending ......................................................................................... 429
14.4.1 Overview.............................................................................................................. 431
14.4.2 Register Descriptions ........................................................................................... 432
14.4.3 Operation ............................................................................................................. 435
14.4.4 Compare-Match ................................................................................................... 436
14.5.1 Example of DMA Transfer between A/D Converter and External Memory
14.5.2 Example of DMA Transfer between External Memory and SCIF Transmitter
(Address Reload on) ............................................................................................ 438
(Indirect Address on) ........................................................................................... 439
.......................................... 379