HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 455

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 2—Address Error Flag (AE): AE indicates that an address error occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended. The CPU
cannot write 1 to this bit. This bit can only be cleared by writing of 0 after reading of 1.
Bit 2: AE
0
1
Bit 1—NMI Flag (NMIF): NMIF indicates that an NMI interrupt occurred. This bit is set both in
operating state and in halt state. The CPU cannot write 1 to this bit. This bit can only be cleared
by writing of 0 after reading of 1.
Bit 1: NMIF
0
1
Bit 0—DMA Master Enable (DME): DME enables or disables DMA transfer for all channels. If
the DME bit and the DE bit corresponding to each channel in CHCR are set to 1, transfer is
enabled in the corresponding channel. If this bit is cleared during transfer, transfer in all the
channels can be terminated.
Even if the DME bit is set, transfer is not enabled when the TE bit is 1 or the DE bit is 0 in CHCR,
or the NMIF bit is 1 in DMAOR.
Bit 0: DME
0
1
Description
No DMAC address error. DMA transfer is enabled.
Clear conditions: When this bit is written with 0 after it is read as 1
DMAC address error. DMA transfer is disabled.
Setting condition: When a DMAC address error occurred
Description
No NMI input. DMA transfer is enabled.
Clear conditions: When this bit is written with 0 after it is read as 1
NMI input. DMA transfer is disabled.
Setting condition: When an NMI interrupt is generated
Description
Disable DMA transfer for all channels
Enable DMA transfer for all channels
By a power-on reset
By a manual reset
By a power-on reset
By a manual reset
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 397 of 1036
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)