HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 89

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

2.1.3
The SH7727 has four system registers, MACL, MACH, PR and PC (figure 2.6).
DSR, A0, X0, X1, Y0 and Y1 registers are also treated as system registers. So, data transfer
instructions between general registers and system registers are supported for them.
2.1.4
The SH7727 has eight data registers and one control register (figure 2.7). The data registers are
32-bit width with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits
(fields A0G and A1G), giving them a total width of 40 bits.
Three types of operations access the DSP data registers. First one is the DSP data. When a DSP
fixed-point data operation uses A0 or A1 for source register, it uses the guard bits (bits 39 to 32).
When it uses A0 or A1 for destination register, bits 39 to 32 in the guard bit are valid. When a
DSP fixed-point data operation uses the DSP registers other than A0 and A1 for source register, it
sign-extends the source value to bits 39 to 32. When it uses them for destination register, the bits
39 to 32 of the result is discard.
Second one is X and Y data transfer operation,
the X and Y memories through 16-bit X and Y data buses (figure 2.8). Registers to be loaded or
stored by this operation are always upper 16 bits (bits 31 to 16). X0 and X1 can be destination of
the X memory load and Y0 and Y1 can be destination of Y memory load, but other register cannot
be destination register of this operation.
31
31
31
System Registers
DSP Registers
MACH
MACL
PR
PC
Figure 2.6 System Registers
0
0
0
Multiply and accumulate high and low registers
(MACH/L)
Store the results of multiplicationand accumulation
operations.
Procedure register (PR)
Stores the subroutine procedure return address.
Program counter (PC)
Indicates the starting address that is four addresses ahead.
“
MOVX.W MOVY.W”. This operation accesses
Rev.6.00 Mar. 27, 2009 Page 31 of 1036
REJ09B0254-0600
Section 2 CPU