HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 711

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6. Transmit/receive reset execution
7. Using the control data interface (slot position)
8. Serial IO (SIOF) reception operation
When using the SIOF again after a transmit/receive operation ends, or after erroneous
operation occurs, first execute a transmit reset (TXRST) or receive reset (RXRST).
Loss of transmit or control data may occur if transmit and control data are mixed within a
single frame during a transmit operation in any of the following modes:
(1) Master mode with an external clock (SIOMCLK) used as the master clock
(2) Slave mode
Therefore, the control data interface (slot position) should be used under the following
conditions:
(1) Master mode
(2) Master clock: Peripheral clock (PCLK)
During serial IO (SIOF) operation, if reception is performed with a slot length of 8 bits and
LSB first, unwanted data is added at the start of the reception data, FIFO storage is delayed
one byte at a time, and the final portion of the data remains in the shift register. To prevent
this, use one of the three methods described below.
(1) Perform reception using a slot length of 8 bits and LSB first, and read and discard the
(2) Perform reception using a slot length of 8 bits and MSB first, then use software processing
(3) Perform reception using a slot length of 16 bits and LSB first, and read only the required
unwanted data.
Read and discard the unwanted data at the start of the reception data. Then, input a dummy
FS after the final portion of data so that the real final portion of data is stored in the FIFO.
This will ensure that reception operates correctly when a slot length of 8 bits and LSB first
is used.
to convert the data to LSB-first format.
Data reception operates correctly when a slot length of 8 bits and MSB first is used. After
receiving the data in MSB-first format, use software processing to convert the data read
from the FIFO from MSB-first to LSB-first format. The result can then be used as 8-bit slot
length LSB-first data.
data.
Data reception operates correctly when a slot length of 16 bits and LSB first is used. Then
one of the following two methods can be used to obtain data that can be used as 8-bit slot
length LSB-first data.
(a) Make settings on the transmitting side so that only the upper 8 bits are used for actual
data. Then, after the 16-bit data is received by the SH7727, extract the upper 8 bits and
use it as 8-bit slot length LSB-first data.
Rev.6.00 Mar. 27, 2009 Page 653 of 1036
Section 20 Serial IO (SIOF)
REJ09B0254-0600