HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 29

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

18.2 Register Descriptions ........................................................................................................ 546
18.3 Operation........................................................................................................................... 548
18.4 Usage Notes ...................................................................................................................... 561
Section 19 Serial Communication Interface with FIFO (SCIF)
19.1 Overview........................................................................................................................... 565
19.2 Register Descriptions ........................................................................................................ 570
19.3 Operation........................................................................................................................... 589
19.4 SCIF Interrupts.................................................................................................................. 600
19.5 Usage Notes ...................................................................................................................... 601
18.1.2 Block Diagram..................................................................................................... 544
18.1.3 Pin Configuration................................................................................................. 545
18.1.4 Register Configuration......................................................................................... 545
18.2.1 Smart Card Mode Register (SCSCMR) ............................................................... 546
18.2.2 Serial Status Register (SCSSR)............................................................................ 547
18.3.1 Overview.............................................................................................................. 548
18.3.2 Pin Connections ................................................................................................... 549
18.3.3 Data Format ......................................................................................................... 549
18.3.4 Register Settings .................................................................................................. 551
18.3.5 Clock.................................................................................................................... 552
18.3.6 Data Transmission and Reception........................................................................ 555
18.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode.................... 561
18.4.2 Retransmission (Receive and Transmit Modes)................................................... 563
19.1.1 Features................................................................................................................ 565
19.1.2 Block Diagram..................................................................................................... 566
19.1.3 Pin Configuration................................................................................................. 568
19.1.4 Register Configuration......................................................................................... 569
19.2.1 Receive Shift Register 2 (SCRSR2)..................................................................... 570
19.2.2 Receive FIFO Data Register 2 (SCFRDR2) ........................................................ 570
19.2.3 Transmit Shift Register 2 (SCTSR2) ................................................................... 571
19.2.4 Transmit FIFO Data Register 2 (SCFTDR2) ....................................................... 571
19.2.5 Serial Mode Register 2 (SCSMR2)...................................................................... 572
19.2.6 Serial Control Register 2 (SCSCR2).................................................................... 574
19.2.7 Serial Status Register 2 (SCSSR2)....................................................................... 576
19.2.8 Bit Rate Register 2 (SCBRR2)............................................................................. 580
19.2.9 FIFO Control Register 2 (SCFCR2) .................................................................... 586
19.2.10 FIFO Data Count Set Register 2 (SCFDR2) ........................................................ 588
19.3.1 Overview.............................................................................................................. 589
19.3.2 Serial Operation ................................................................................................... 590
Rev.6.00 Mar. 27, 2009 Page xxvii of lvi
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REJ09B0254-0600