HD6417727F100C Renesas Electronics America, HD6417727F100C Datasheet - Page 848

• Manufacturer Part Number: HD6417727F100C
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100C

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 LCD Controller
25.3
25.3.1
This LCDC is capable of controlling displays with up to 1024 × 1024 dots and 16 bpp (bits per
pixel). The image data for display is stored in system memory, which is shared with the CPU.
This LCDC should read the data from system memory between display periods.
The SH7727 has a maximum 32-burst memory read operation and a 2.4-kbyte line buffer, so
although a complete breakdown of the display is unlikely, there may be some problems with the
display depending on the combination.
The bus-occupancy rate described below should not, as a rule, exceed 40%.
Bus-occupancy rate (%) =
The overhead coefficient depends on the bus used by the SDRAM in CL2, as indicated below.
If the hardware rotation function is not used (ROT = 0), the overhead coefficient is 1.375 if a 32-
bit bus is used and 1.188 if a 16-bit bus is used.
If the hardware rotation function is used (ROT = 1), the overhead coefficient is determined by the
access unit select (AU) setting and the bus width, as follows.
Access Unit Select (AU) Setting
4-burst operation
8-burst operation
16-burst operation
32-burst operation
Rev.6.00 Mar. 27, 2009 Page 790 of 1036
REJ09B0254-0600
Operation
LCD Module Sizes which can be Displayed in this LCDC
Overhead coefficient × total number of display pixels ((HDCN + 1) × 8 × (VDLN + 1)) ×
frame rate (Hz) × number of colors (bpp) × 100
32-Bit Bus
2.500
1.750
1.375
1.188
CKIO (Hz) × bus width (bits)
16-Bit Bus
1.750
1.375
1.188
1.094