UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 234

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.6.3 Example of controlling subsystem clock
232
The following describes examples of setting procedures for the following cases.
(1) When oscillating subsystem clock
(2) When using subsystem clock as CPU clock
(3) When stopping subsystem clock
Caution The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
(1) Example of setting procedure when oscillating the subsystem clock
The subsystem clock can be oscillated by connecting a crystal resonator to the XT1 and XT2 pins.
When the subsystem clock is not used, the XT1/P123 and XT2/P124 pins can be used as input port pins.
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to the
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition, stop
<1> Setting P123/XT1 and P124/XT2 pins (CMC register)
<2> Controlling oscillation of subsystem clock (CSC register)
<3> Waiting for the stabilization of the subsystem clock oscillation
Caution The CMC register can be written only once after reset release, by an 8-bit memory
<2> Stopping the internal high-speed oscillation clock (CSC register)
Remark For setting of the P121/X1 and P122/X2 pins, see 6.6.1 Example of controlling high-speed
If XTSTOP is cleared to 0, the XT1 oscillator starts oscillating.
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
peripheral hardware (except the real-time counter, clock output/buzzer output, and watchdog
timer). At this time, the operations of the A/D converter and IIC0 are not guaranteed. For the
operating characteristics of the peripheral hardware, refer to the chapters describing the various
peripheral hardware as well as CHAPTER 29
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS).
EXCLK
When HIOSTOP is set to 1, internal high-speed oscillation clock is stopped.
0/1
peripheral hardware that is operating on the internal high-speed oscillation clock.
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the same
time. For EXCLK and OSCSEL bits, see 6.6.1 (1) Example of setting procedure when
oscillating the X1 clock or 6.6.1 (2) Example of setting procedure when using the external
main system clock.
system clock.
OSCSEL
0/1
0
0
CHAPTER 6 CLOCK GENERATOR
User’s Manual U18432EJ5V0UD
OSCSELS
1
0
0
ELECTRICAL SPECIFICATIONS (STANDARD
0
0
0
0
AMPH
0/1