UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 965

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4th edition
Edition
Change of (b) Serial output enable register m (SOEm) in Figure 13-76 Example
of Contents of Registers for UART Reception of UART (UART0, UART1, UART2,
UART3)
Modification of Figure 13-80 Timing Chart of UART Reception
Modification of transfer data length in 13.6.3 LIN transmission
Change of Note 2 in Figure 13-82 Transmission Operation of LIN
Change of Note 2 in Table 13-3 Selection of Operation Clock
Addition of Note to 13.7 Operation of Simplified I
Communication
Addition of Note to 13.7.1 Address field transmission
Change of Figure 13-89 Initial Setting Procedure for Address Field
Transmission
Change of Figure 13-90 Timing Chart of Address Field Transmission
Addition of Note to 13.7.2 Data transmission
Change of Figure 13-93 Timing Chart of Data Transmission
Addition of Note to 13.7.3 Data reception
Change of Figure 13-96 Timing Chart of Data Reception
Change of Figure 13-97 Flowchart of Data Reception and change of Caution
Change of Figure 13-98 Timing Chart of Stop Condition Generation
Change of Note 2 in Table 13-4 Selection of Operation Clock
Change of Note in Figure 14-6 Format of IIC Control Register 0 (IICC0)
Change of Table 14-2 Selection Clock Setting
Change of Table 14-3 Selection Clock Setting
Change of Table 14-5 Extension Code Bit Definitions
Change of Figure 14-24 Master Operation in Single-Master System
Change of Figure 14-25 Master Operation in Multi-Master System
Change of Figure 14-26 Slave Operation Flowchart
Change of Figures 14-28 and 14-29
Change of Figure 16-5 Format of DMA Operation Control Register n (DRCn)
Addition of Note to Table 16-2 Response Time of DMA Transfer
Change of description in 17.2 Interrupt Sources and Configuration
Change of Table 17-1 Interrupt Source List
Change of Caution 2 in 18.3 (1) Key return mode register (KRM)
APPENDIX C REVISION HISTORY
User’s Manual U18432EJ5V0UD
Description
2
C (IIC10, IIC11, IIC20, IIC21)
CHAPTER 13 SERIAL
ARRAY UNIT
(continuation)
CHAPTER 14 SERIAL
INTERFA CE IIC0
CHAPTER 16 DMA
CONTROLLER
CHAPTER 17
INTERRUPT
FUNCTIONS
CHAPTER 18 KEY
INTERRUPT
FUNCTION
Chapter
(11/13)
963