UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 451

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
(Essential)
(Selective)
Figure 13-27. Procedure for Resuming Master Transmission
Changing setting of SPSm register
Changing setting of SMRmn register
Changing setting of SDRmn register
Changing setting of SCRmn register
Changing setting of SOEm register
Changing setting of SOEm register
Changing setting of SOm register
Starting setting for resumption
Starting communication
Writing to SSm register
Clearing error flag
Port manipulation
Port manipulation
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U18432EJ5V0UD
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Disable data output and clock output of
the target channel by setting a port
register and a port mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Set the SOEm register and enable data
output of the target channel.
SEmn = 1 when the SSmn bit of the
target channel is set to 1.
Sets transmit data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
Set the SOEm register and stop the
output of the target channel.
449