UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 776

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
774
Instruction
8-bit
operation
Group
2.
3.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
Mnemonic
ADDC
SUB
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
When the program memory area is accessed.
Except r = A
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
register (CKC).
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, ES:!addr16
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, ES:!addr16
A, ES:[HL]
A, ES:[HL + byte]
A, ES:[HL + B]
A, ES:[HL + C]
Operands
Note 3
Note 3
Table 28-5. Operation List (7/17)
CHAPTER 28 INSTRUCTION SET
Bytes
2
3
2
2
2
3
1
2
2
2
4
2
3
3
3
2
3
2
2
2
3
1
2
2
2
4
2
3
3
3
User’s Manual U18432EJ5V0UD
Note 1 Note 2
1
2
1
1
1
1
1
1
1
1
2
2
2
2
2
1
2
1
1
1
1
1
1
1
1
2
2
2
2
2
Clocks
−
−
−
−
−
4
4
4
4
4
5
5
5
5
5
−
−
−
−
−
4
4
4
4
4
5
5
5
5
5
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
r, CY ← r + A + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A + (HL + B) + CY
A, CY ← A + (HL + C) + CY
A, CY ← A + (ES, addr16) + CY
A, CY ← A + (ES, HL) + CY
A, CY ← A + ((ES, HL) + byte) + CY
A, CY ← A + ((ES, HL) + B) + CY
A, CY ← A + ((ES, HL) + C) + CY
A, CY ← A − byte
(saddr), CY ← (saddr) − byte
A, CY ← A − r
r, CY ← r − A
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, CY ← A − (HL + byte)
A, CY ← A − (HL + B)
A, CY ← A − (HL + C)
A, CY ← A − (ES:addr16)
A, CY ← A − (ES:HL)
A, CY ← A − ((ES:HL) + byte)
A, CY ← A − ((ES:HL) + B)
A, CY ← A − ((ES:HL) + C)
CPU
) selected by the system clock control
Operation
Z AC CY
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