UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 331

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TAU
default
setting
Channel
default
setting
Operat
ion
start
Figure 7-71. Operation Procedure When Multiple PWM Output Function Is Used (1/2)
Remark
Sets slave channel.
Sets TOEmp and TOEmq (slave) to 1 (only when
operation is resumed).
The TSmn bit (master), and TSmp and TSmq (slave)
bits of the TSm register are set to 1 at the same time.
Sets the TAU0EN bit, TAU1EN bit of the PER0 register
to 1.
Sets the TPSm register.
Sets the TMRmn, TMRmp, and TMRmq registers of
each channel to be used (determines operation mode of
channels).
An interval (period) value is set to the TDRmn register of
the master channel, and a duty factor is set to the
TDRmp and TDRmq registers of the slave channel.
Determines clock frequencies of CKm0 and CKm1.
The TOMmp and TOmq bits of the TOMm register is
set to 1 (combination-operation mode).
Clears the TOLmp and TOLmq bits to 0.
Sets the TOmp and TOmq bits and determines default
level of the TOmp and TOmq outputs.
Sets TOEmp and TOEmq to 1 and enables operation
of TOmp and TOmq.
Clears the port register and port mode register to 0.
m: Unit number(m = 0, 1), n: Channel number, p: Slave channel number 1 (n+1)
q: Slave channel number 2 (n+2)
When m = 0
When m = 1
The TSmn, TSmp, and TSmq bits automatically
return to 0 because they are trigger bits.
n = 0, 2, 4
n < p < q ≤ 7 (where p and q are a consecutive integer greater than n)
n = 0
n < p < q ≤ 3 (where p and q are a consecutive integer greater than n ( p = 1, q = 2))
Software Operation
CHAPTER 7 TIMER ARRAY UNIT
User’s Manual U18432EJ5V0UD
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOmp and TOmq pins go into Hi-Z output state.
The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
TOmp or TOmq does not change because channel stops
operating.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
TEmn = 1, TEmp, TEmq = 1
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
When the master channel starts counting, INTTMmn
is generated. Triggered by this interrupt, the slave
channel also starts counting.
Hardware Status
329