UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 307

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.7.5 Operation as input signal high-/low-level width measurement
(high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the
following expression.
status is set.
counter counts up in synchronization with the count clock. When the valid capture edge (falling edge of TImn when
the high-level width is to be measured) is detected later, the count value is transferred to TDRmn and, at the same
time, INTTMmn is output. If the counter overflows at this time, the OVF bit of the TSRmn register is set to 1. If the
counter does not overflow, the OVF bit is cleared. TCRmn stops at the value “value transferred to TDRmn + 1”, and
the TImn pin start edge detection wait status is set. After that, the above operation is repeated.
updated depending on whether the counter overflows during the measurement period. Therefore, the overflow status
of the captured value can be checked.
bit of the TSRmn register is set to 1. However, the OVF bit is configured as an integral flag, and the correct interval
value cannot be measured if an overflow occurs more than once.
CISmn1 and CISmn0 bits of the TMRmn register.
TEmn is 1.
By starting counting at one edge of TImn and capturing the number of counts at another edge, the signal width
TCRmn operates as an up counter in the capture & one-count mode.
When the channel start trigger (TSmn) is set to 1, TEmn is set to 1 and the TImn pin start edge detection wait
When the TImn start valid edge (rising edge of TImn when the high-level width is to be measured) is detected, the
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
Whether the high-level width or low-level width of the TImn pin is to be measured can be selected by using the
Because this function is used to measure the signal width of the TImn pin input, TSmn cannot be set to 1 while
CISmn1, CISmn0 of TMRmn = 10B: Low-level width is measured.
CISmn1, CISmn0 of TMRmn = 11B: High-level width is measured.
Operation
Signal width of TImn input = Period of count clock × ((10000H × TSRn: OVF) + (Capture value of TDRmn + 1))
Remark
TImn pin
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of the
Figure 7-53. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
clock
CKm1
CKm0
TMRmn register, so an error equal to the number of operating clocks occurs.
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7),
mn = 00 to 07, 10 to 13
detection
Edge
CHAPTER 7 TIMER ARRAY UNIT
User’s Manual U18432EJ5V0UD
Timer counter
Data register
(TCRmn)
(TDRmn)
controller
Interrupt
Interrupt signal
(INTTMmn)
305