UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 956

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

954
2nd edition
Edition
Addition of Notes 3 and change of Cautions 2 in Figure 6-6. Format of System
Clock Control Register (CKC)
Addition of Cautions 5 to Figure 6-8. Format of Operation Speed Mode Control
Register (OSMC)
Change of description in 6.3 (8) Internal high-speed oscillator trimming register
(HIOTRM) and addition of Caution
Change of Figure 6-9. Format of Internal High-Speed Oscillator Trimming
Register (HIOTRM) and addition of Caution
Change of Figure 6-13. Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
Change of Table 7-1. Configuration of Timer Array Unit 0
Change of Table 7-2. Configuration of Timer Array Unit 1
Addition of Note to Figure 7-6. Format of Timer Clock Select Register m (TPSm)
Change of description of MASTERmn bit in Figure 7-7. Format of Timer Mode
Register mn (TMRmn) (1/3)
Change of Table 7-3. OVF Bit Operation and Set/Clear Conditions in Each
Operation Mode and addition of Remark
Addition of Caution to Figure 7-17. Format of Timer Input Select Register m
(TISm)
Addition of description to 7.3 (10) Timer output register m (TOm)
Addition of description to 7.3 (12) Timer output mode register m (TOMm)
Change of Remark in Figure. 7-22. Format of Input Switch Control Register
(ISC)
Change of description in 7.3 (14) Noise filter enable register 1, 2 (NFEN1, NFEN2)
Change of 7.5.1 TImn edge detection circuit
Change of Figure 8-1. Block Diagram of Real-Time Counter
Change of Caution in Figure 8-2. Format of Peripheral Enable Register 0 (PER0)
Addition of description to 8.3 (15) Alarm hour register (ALARMWH)
Addition of Note to Figure 8-18. Procedure for Starting Operation of Real-Time
Counter
Change of Cautions 1 and Cautions 2 in 9.3 (1) Watchdog timer enable register
(WDTE)
Addition of Caution 3 to Table 9-4. Setting Window Open Period of Watchdog
Timer
Change of Figure 13-1. Block Diagram of Serial Array Unit 0
Change of Figure 13-2. Block Diagram of Serial Array Unit 1
Addition of settings and Note to Figure 13-5. Format of Serial Clock Select
Register m (SPSm)
Addition of Note to Figure 13-7. Format of Serial Communication Operation
Setting Register mn (SCRmn) (2/3)
Change of Figure 13-14. Format of Serial Output Enable Register m (SOEm)
Addition of description to 13.3 (12) Serial output register m (SOm)
Change of Figure 13-15. Format of Serial Output Register m (SOm)
Addition of 13.4 Operation stop mode
Addition of Note to transfer rate
Change of description to (a) Serial output register m (SOm)
Change of Figure 13-27. Procedure for Resuming Master Transmission
APPENDIX C REVISION HISTORY
User’s Manual U18432EJ5V0UD
Description
CHAPTER 6 CLOCK
GENERATOR
CHAPTER 7 TIMER
ARRAY UNIT
CHAPTER 8 REAL-
TIME COUNTER
CHAPTER 9
WATCHDOG TIMER
CHAPTER 13 SERIAL
ARRAY UNIT
Chapter
(2/13)