UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 718

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Port mode register 12 (PM12)
22.4 Operation of Low-Voltage Detector
(1) Used as reset (LVIMD = 1)
(2) Used as interrupt (LVIMD = 0)
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
716
The low-voltage detector can be used in the following two modes.
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
Remark LVIMD: Bit 1 of low-voltage detection register (LVIM)
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this
time, the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
signal when V
generates an internal reset signal when EXLVI < V
Remark The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to
V
V ±0.1 V). When EXLVI drops lower than V
(EXLVI ≥ V
Address: FFF2CH
Symbol
LVI
PM12
(V
DD
LVISEL: Bit 2 of LVIM
< V
raise the power supply from the POC detection voltage or lower, the internal reset signal is
generated when the supply voltage (V
internal reset signal is generated when the supply voltage (V
±0.1 V).
EXLVI
PM120
LVI
DD
7
1
) or when V
0
1
), generates an interrupt signal (INTLVI).
< V
After reset: FFH
LVI
, and releases internal reset when V
Output mode (output buffer on)
Input mode (output buffer off)
Figure 22-4. Format of Port Mode Register 12 (PM12)
6
1
DD
becomes V
CHAPTER 22 LOW-VOLTAGE DETECTOR
R/W
5
1
User’s Manual U18432EJ5V0UD
LVI
or higher (V
EXLVI
DD
DD
DD
P120 pin I/O mode selection
4
1
) and detection voltage (V
EXLVI
(EXLVI < V
) and detection voltage (V
) < detection voltage (V
, and releases internal reset when EXLVI ≥ V
DD
≥ V
DD
≥ V
3
1
LVI
EXLVI
), generates an interrupt signal (INTLVI).
LVI
) or when EXLVI becomes V
.
DD
2
1
LVI
) < detection voltage (V
LVI
= 2.07 V ±0.2 V). After that, the
LVI
). When V
), generates an internal reset
1
1
DD
PM120
drops lower than
0
EXLVI
LVI
EXLVI
EXLVI
or higher
= 2.07 V
.
= 1.21
EXLVI
),