Z8F6401AN020SC00TR Zilog, Z8F6401AN020SC00TR Datasheet - Page 130

• Manufacturer Part Number: Z8F6401AN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44LQFP
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401AN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401AN020SC00T

PS017609-0803
Note:
I
Start and Stop Conditions
Writing a Transaction with a 7-Bit Address
2
C Interrupts
Writing to the I
limit to the amount of data transferred in one operation. When transmitting data or
acknowledging read data from the slave, the SDA signal changes in the middle of the low
period of SCL and is sampled in the middle of the high period of SCL.
the I
Acknowledge (NAK) interrupts. NAK interrupts occur when a Not Acknowledge is
received from the slave or sent by the I
source sets bit 0 and can only be cleared by setting the Start or Stop bit. When this inter-
rupt occurs, the I
interrupt service routine, this interrupt must be the first thing polled. Receive interrupts
occur when a byte of data has been received by the I
reading from the I
interrupt is cleared before performing any other action.
For Transmit interrupts to occur, the TXI bit must be 1 in the I
mit interrupts occur under the following conditions when the transmit data register is
empty:
•
•
•
•
•
The master (I
transaction, the I
low while SCL is high. Then a high-to-low transition occurs on the SDA signal while the
clock is High. To complete a transaction, the I
creating a low-to-high transition of the SDA signal in the middle of the high period of the
SCL signal.When the SCL signal is High, the master generates a Start bit by pulling a
High SDA signal Low and generates a Stop bit by releasing the SDA signal. The Start and
Stop signals are found in the I
the Z8F640x family device must begin or end a transaction.
1. The I
The I
The START bit is set and there is no valid data in the I
shift out.
The first bit of the byte of an address is shifting out and the RD bit of the I
register is deasserted.
The first bit of a 10-bit address shifts out.
The first bit of write data shifted out.
2
C Controller contains three sources of interrupts—Transmit, Receive and Not
2
2
C Controller is idle (not performing an operation).
C Controller shifts the I
2
C) drives all Start and Stop signals and initiates all transactions. To start a
2
C Data register always clears a Transmit interrupt.
2
2
C Controller generates a START condition by pulling the SDA signal
C Controller waits until it is cleared before performing any action. In an
2
C Data register. If no action is taken, the I
2
C Control register and must be written by software when
2
C Shift register out onto SDA signal.
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
2
C Controller and the Start or Stop bit is set. This
2
C Controller generates a Stop condition by
2
C master. This interrupt is cleared by
2
C Shift or I
2
C Controller waits until this
2
C Control register. Trans-
2
C Data register to
Z8 Encore!
I2C Controller
2
C Status
®
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