Z8F6401AN020SC00TR Zilog, Z8F6401AN020SC00TR Datasheet - Page 172

• Manufacturer Part Number: Z8F6401AN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44LQFP
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401AN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401AN020SC00T

PS017610-0404
START
OCD Data Format
OCD Auto-Baud Detector/Generator
•
•
•
•
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1.5 Stop bits
(Figure 89)
Figure 89. OCD Data Format
To run over a range of baud rates (data bits per second) with various system clock frequen-
cies, the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD
is idle until it receives data. The OCD requires that the first character sent from the host is
the character
data bits). The Auto-Baud Detector measures this period and sets the OCD Baud Rate
Generator accordingly.
The Auto-Baud Detector/Generator is clocked by the Z8F640x family device system
clock. The minimum baud rate is the system clock frequency divided by 512. For optimal
operation, the maximum recommended baud rate is the system clock frequency divided by
8. The theoretical maximum baud rate is the system clock frequency divided by 4. This
theoretical maximum is possible for low noise designs with clean signals. Table 92 lists
minimum and recommended maximum baud rates for sample crystal frequencies.
Table 92. OCD Baud-Rate Limits
D0
System Clock Frequency
Power-on reset
Voltage Brownout reset
Asserting the RESET pin Low to initiate a Reset.
Driving the DBG pin Low while the Z8F640x family device is in Stop mode initiates a
System Reset.
0.032768 (32KHz)
(MHz)
D1
20.0
1.0
80H
. The character
D2
Recommended Maximum Baud Rate
D3
80H
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
has eight continuous bits Low (one Start bit plus 7
(kbits/s)
D4
125.0
4.096
2500
D5
D6
Minimum Baud Rate
On-Chip Debugger
D7
(kbits/s)
0.064
39.1
1.96
Z8 Encore!
STOP
®
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