Z8F6401AN020SC00TR Zilog, Z8F6401AN020SC00TR Datasheet - Page 174

• Manufacturer Part Number: Z8F6401AN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44LQFP
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401AN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401AN020SC00T

On-Chip Debugger Commands
Table 93. On-Chip Debugger Commands
PS017610-0404
Debug Command
Read OCD Revision
Reserved
Read OCD Status Register
Read Runtime Counter
Write OCD Control Register
Read OCD Control Register
Write Program Counter
Read Program Counter
Write Register
Read Register
Runtime Counter
ister. When the Watchpoint event occurs, the Z8F640x family device enters Debug mode
and the DBGMODE bit in the OCDCTL register becomes 1.
The On-Chip Debugger contains a 16-bit Runtime Counter. It counts system clock cycles
between Breakpoints. The counter starts counting when the On-Chip Debugger leaves
Debug mode and stops counting when it enters Debug mode again or when it reaches the
maximum count of
The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation of the Z8F640x family device, only a subset of
the OCD commands are available. In Debug mode, all OCD commands become available
unless the user code and control registers are protected by programming the Read Protect
Option Bit (RP). The Read Protect Option Bit prevents the code in memory from being
read out of the Z8F640x family device. When this option is enabled, several of the OCD
commands are disabled. Table 93 contains a summary of the On-Chip Debugger com-
mands. Each OCD command is described in further detail in the bulleted list following
Table 93. Table 93 indicates those commands that operate when the Z8F640x family
device is not in Debug mode (normal operation) and those commands that are disabled by
programming the Read Protect Option Bit.
Command Byte
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
FFFFH
.
Enabled when NOT
in Debug mode?
Yes
Yes
Yes
Yes
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
-
-
-
-
-
-
registers are allowed. Additionally, only the
Only writes of the Flash Memory Control
Mass Erase command is allowed to be
written to the Flash Control register.
Cannot clear DBGMODE bit
Read Protect Option Bit
Disabled by
Disabled
Disabled
Disabled
-
-
-
-
-
On-Chip Debugger
Z8 Encore!
®
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