Z8F6401AN020SC00TR Zilog, Z8F6401AN020SC00TR Datasheet - Page 138

• Manufacturer Part Number: Z8F6401AN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44LQFP
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401AN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401AN020SC00T

PS017609-0803
START—Send Start Condition
This bit sends the Start condition. Once asserted, it is cleared by the I
sends the START condition or by deasserting the IEN bit. After this bit is set, the Start
condition is sent if there is data in the I
one of these registers, the I
the I
and the acknowledge phase completed. If the STOP bit is also set, it also waits until the
STOP condition is sent before the START condition. If this bit is 1, it cannot be cleared to
0 by writing to the register.This bit clears when the I
STOP—Send Stop Condition
This bit causes the I
register has completed transmission or after a byte has been received in a receive opera-
tion. Once set, this bit is reset by the I
by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the regis-
ter.This bit clears when the I
BIRQ—Baud Rate Generator Interrupt Request
This bit causes an interrupt to occur every time the baud rate generator counts down to
zero. This bit allows the I
being used elsewhere. This bit must only be set when the I
TXI—Enable TDRE interrupts
This bit enables interrupts when the I
NAK—Send NAK
This bit sends a Not Acknowledge condition after the next byte of data has been read from
the I
bit is deasserted.
FLUSH—Flush Data
Setting this bit to 1 clears the I
flushing of the I
the I
FILTEN—I
Setting this bit to 1 enables low-pass digital filters on the SDA and SCL input signals.
These filters reject any input pulse with periods less than a full system clock cycle. The fil-
ters introduce a 3-system clock cycle latency on the inputs.
2
2
2
C Controller is shifting out data, it generates a START condition after the byte shifts
C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN
C Data register. Reading this bit always returns 0.
2
C Signal Filter Enable
2
C Data register when an NAK is received after the data has been sent to
2
C Controller to issue a Stop condition after the byte in the I
2
C Controller to be used as an additional counter when it is not
2
C Controller waits until data is loaded. If this bit is set while
2
C is disabled.
2
C Data register and sets the TDRE bit to 1. This bit allows
2
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
2
C Data register is empty on the I
C Controller after a Stop condition has been sent or
2
C Data or I
2
C Shift register. If there is no data in
2
C is disabled.
2
C Controller is disabled.
2
C Controller after it
2
C Controller.
Z8 Encore!
I2C Controller
2
C Shift
®
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