Z8F042AHJ020SC00TR Zilog, Z8F042AHJ020SC00TR Datasheet - Page 103

• Manufacturer Part Number: Z8F042AHJ020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHJ020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHJ020SC00T

PS022825-0908
Watchdog Timer Refresh
Watchdog Timer Time-Out Response
When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer
Reload registers. The Watchdog Timer counts down to
instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the
downcounter to be reloaded with the WDT Reload value stored in the Watchdog Timer
Reload registers. Counting resumes following the reload operation.
When the Z8 Encore! XP
the on-chip debugger), the Watchdog Timer is continuously refreshed to prevent any
Watchdog Timer time-outs.
The Watchdog Timer times out when the counter reaches
Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash
Option Bit determines the time-out response of the Watchdog Timer. For information on
programming the WDT_RES Flash Option Bit, see
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Reset
Status (RSTSTAT) register (see
enabled, the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer
interrupt vector and executing code from the vector address. After time-out and interrupt
generation, the Watchdog Timer counter rolls over to its maximum value of
continues counting. The Watchdog Timer counter is not automatically returned to its
Reload Value.
The Reset Status (RSTSTAT) register must be read before clearing the WDT interrupt.
This read clears the WDT timeout Flag and prevents further WDT interrupts from
immediately occurring.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP
F082A Series devices are in STOP mode, the Watchdog Timer automatically initiates a
Stop Mode Recovery and generates an interrupt request. Both the WDT status bit and the
STOP bit in the Reset Status (RSTSTAT) register are set to 1 following a WDT time-out in
STOP mode. For more information on Stop Mode Recovery, see
ery, and Low Voltage Detection
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-
cuting code from the vector address.
®
F082A Series devices are operating in DEBUG mode (using
Reset Status Register
on page 23.
Flash Option Bits
on page 30). If interrupts are
000000H
Z8 Encore! XP
000000H
Product Specification
Reset, Stop Mode Recov-
unless a WDT
. A time-out of the
on page 153.
®
F082A Series
Watchdog Timer
FFFFFH
and
92