Z8F042AHJ020SC00TR Zilog, Z8F042AHJ020SC00TR Datasheet - Page 195

• Manufacturer Part Number: Z8F042AHJ020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHJ020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHJ020SC00T

Table 106. OCD Control Register (OCDCTL)
On-Chip Debugger Control Register Definitions
BITS
FIELD
RESET
R/W
PS022825-0908
OCD Control Register
DBGMODE
R/W
7
0
The OCD Control register controls the state of the On-Chip Debugger. This register is
used to enter or exit DEBUG mode and to enable the
Z8 Encore! XP
A reset and stop function can be achieved by writing
function can be achieved by writing
a run function can be implemented by writing
.
DBGMODE—DEBUG Mode
The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and Breakpoints are enabled. If the
Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
device. It cannot be written to 0.
0 = The Z8 Encore! XP F082A Series device is operating in NORMAL mode.
1 = The Z8 Encore! XP F082A Series device is in DEBUG mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of the
points are disabled and the
bit is 1, when a
automatically set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
BRKEN
If the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled,
this command reads and discards one byte.
DBG
DBG
R/W
6
0
←
←
®
BRK
F082A Series device.
12H
1-5 byte opcode
DBGACK
instruction is decoded, the
R/W
5
0
BRK
instruction behaves similar to an NOP instruction. If this
R
4
0
41H
BRK
to this register. If the device is in DEBUG mode,
instruction (opcode
40H
R
DBGMODE
3
0
Reserved
to this register.
81H
BRK
Z8 Encore! XP
bit of the OCDCTL register is
to this register. A reset and go
instruction. It can also reset the
R
2
0
00H
Product Specification
). By default, Break-
R
1
0
®
On-Chip Debugger
F082A Series
RST
R/W
0
0
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