Z8F042AHJ020SC00TR Zilog, Z8F042AHJ020SC00TR Datasheet - Page 186

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Z8F042AHJ020SC00TR

Manufacturer Part Number
Z8F042AHJ020SC00TR
Description
IC ENCORE XP MCU FLASH 4K 28SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheets

Specifications of Z8F042AHJ020SC00TR

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
23
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Z8F042AHJ020SC00T
PS022825-0908
Figure 25. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
DEBUG Mode
The operating characteristics of the devices in DEBUG mode are:
Entering DEBUG Mode
The operating characteristics of the devices entering DEBUG mode are:
RS-232 TX
RS-232 RX
Note:
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to
execute specific instructions.
The system clock operates unless in STOP mode.
All enabled on-chip peripherals operate unless in STOP mode.
Automatically exits HALT mode.
Constantly refreshes the Watchdog Timer, if enabled.
The device enters DEBUG mode after the eZ8 CPU executes a BRK (Breakpoint)
instruction.
If the DBG pin is held Low during the final clock cycle of system reset, the part enters
DEBUG mode immediately (20-/28-pin products only).
Holding the DBG pin Low for an additional 5000 (minimum) clock cycles
after reset (making sure to account for any specified
frequency error if using an internal oscillator) prevents a false
interpretation of an Autobaud sequence (see
Generator
Transceiver
RS-232
on page 176).
Open-Drain
Buffer
VDD
Z8 Encore! XP
10 k
Ω
OCD Auto-Baud Detector/
DBG Pin
Product Specification
®
On-Chip Debugger
F082A Series
175

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