Z8F042AHJ020SC00TR Zilog, Z8F042AHJ020SC00TR Datasheet - Page 89

• Manufacturer Part Number: Z8F042AHJ020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHJ020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHJ020SC00T

PS022825-0908
Follow the steps below for configuring a timer for CAPTURE mode and initiating the
count:
1. Write to the Timer Control register to:
2. Write to the Timer High and Low Byte registers to set the starting count value
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these
5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control register to enable the timer and initiate counting.
In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
CAPTURE RESTART Mode
In CAPTURE RESTART mode, the current timer count value is recorded when the accept-
able external Timer Input transition occurs. The Capture count value is written to the
Timer PWM High and Low Byte Registers. The timer input is the system clock. The
TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or
a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is
generated and the count value in the Timer High and Low Byte registers is reset to
and counting resumes. The INPCAP bit in TxCTL0 register is set to indicate the timer
interrupt is because of an input capture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
–
–
–
–
(typically
registers allows the software to determine if interrupts were generated by either a
capture event or a reload. If the PWM High and Low Byte registers still contain
0000H after the interrupt, the interrupt was generated by a Reload.
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and reload events. If appropriate, configure the timer interrupt to be
generated only at the input capture event or the reload event by setting TICONFIG
field of the TxCTL0 register.
Capture Elapsed Time (s)
Disable the timer.
Configure the timer for CAPTURE mode.
Set the prescale value.
Set the Capture edge (rising or falling) for the Timer Input.
0001H
).
=
(
-------------------------------------------------------------------------------------------------- -
Capture Value
System Clock Frequency (Hz)
–
Start Value
Z8 Encore! XP
)
Product Specification
×
Prescale
®
F082A Series
0001H
Timers
78