Z8F042AHJ020SC00TR Zilog, Z8F042AHJ020SC00TR Datasheet - Page 182

• Manufacturer Part Number: Z8F042AHJ020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHJ020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHJ020SC00T

PS022825-0908
Power Failure Protection
Optimizing NVDS Memory Usage for Execution Speed
read operations to illegal addresses. Also, the user code must pop the address byte off the
stack.
The read routine uses 9 bytes of stack space in addition to the one byte of address pushed
by the user. Sufficient memory must be available for this stack usage.
Because of the Flash memory architecture, NVDS reads exhibit a non-uniform execution
time. A read operation takes between 44 μs and 489 μs (assuming a 20 MHz system
clock). Slower system clock speeds result in proportionally higher execution times.
NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return
0xff. Illegal read operations have a 2 μs execution time.
The status byte returned by the NVDS read routine is zero for successful read, as
determined by a CRC check. If the status byte is non-zero, there was a corrupted value in
the NVDS array at the location being read. In this case, the value returned in R0 is the byte
most recently written to the array that does not have a CRC error.
The NVDS routines employ error checking mechanisms to ensure a power failure
endangers only the most recently written byte. Bytes previously written to the array are
not perturbed.
A system reset (such as a pin reset or Watchdog Timer reset) that occurs during a write
operation also perturbs the byte currently being written. All other bytes in the array are
unperturbed.
The NVDS read time varies drastically, this discrepancy being a trade-off for minimizing
the frequency of writes that require post-write page erases (see
read time of address N is a function of the number of writes to addresses other than N
since the most recent write to address N, as well as the number of writes since the most
recent page erase. Neglecting effects caused by page erases and results caused by the ini-
tial condition in which the NVDS is blank, a rule of thumb is that every write since the
most recent page erase causes read times of unwritten addresses to increase by 1 μs, up to
a maximum of (511-NVDS_SIZE) μs.
Table 104. NVDS Read Time
Operation
Read (16 byte array)
Read (64 byte array)
Minimum
Latency
875
876
Maximum
Latency
9961
8952
Z8 Encore! XP
Table
Product Specification
Non-Volatile Data Storage
104). The NVDS
®
F082A Series
171