Z8F042AHJ020SC00TR Zilog, Z8F042AHJ020SC00TR Datasheet - Page 40

• Manufacturer Part Number: Z8F042AHJ020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHJ020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHJ020SC00T

PS022825-0908
Note:
Caution:
Stop Mode Recovery Using Watchdog Timer Time-Out
Stop Mode Recovery Using a GPIO Port Pin Transition
vector address. Following Stop Mode Recovery, the STOP bit in the Reset Status
(RSTSTAT) Register is set to 1.
ing actions. The text following provides more detailed information about each of the Stop
Mode Recovery sources.
Table 10. Stop Mode Recovery Sources and Resulting Action
If the Watchdog Timer times out during STOP mode, the device undergoes a Stop Mode
Recovery sequence. In the Reset Status (RSTSTAT) register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the Z8 Encore! XP F082A Series device is configured to respond to interrupts, the eZ8
CPU services the Watchdog Timer interrupt request following the normal Stop Mode
Recovery sequence.
Each of the GPIO Port pins may be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery.
The SMR pulses shorter than specified does not trigger a recovery (see
page 229). When this happens, the STOP bit in the Reset Status (RSTSTAT) register is set
to 1.
Operating Mode Stop Mode Recovery Source
STOP mode
In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the Port transition only if the signal stays on the Port pin through
the end of the Stop Mode Recovery delay. As a result, short pulses on the Port pin can
Watchdog Timer time-out when
configured for Reset
Watchdog Timer time-out when
configured for interrupt
Data transition on any GPIO Port
pin enabled as a Stop Mode
Recovery source
Assertion of external
Debug Pin driven Low
Table 10
Reset, Stop Mode Recovery, and Low Voltage Detection
RESET
lists the Stop Mode Recovery sources and result-
Pin
Z8 Encore! XP
Action
Stop Mode Recovery
Stop Mode Recovery followed by
interrupt (if interrupts are
enabled)
Stop Mode Recovery
System Reset
System Reset
Product Specification
®
F082A Series
Table 131
on
29