Z8F042AHJ020SC00TR Zilog, Z8F042AHJ020SC00TR Datasheet - Page 119

• Manufacturer Part Number: Z8F042AHJ020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHJ020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHJ020SC00T

Table 61. UART Control 0 Register (U0CTL0)
UART Control Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS022825-0908
UART Control 0 and Control 1 Registers
TEN
R/W
7
0
(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data
rate is calculated using the following equation:
When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit timer
with interrupt on time-out. Follow the steps below to configure the Baud Rate Generator
as a timer with interrupt on time-out:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register
2. Load the acceptable 16-bit count value into the UART Baud Rate High and Low Byte
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
The UART control registers support the UART and the associated Infrared Encoder/
Decoders. For more information on infrared operation, see
page 117.
The UART Control 0 (UxCTL0) and Control 1 (UxCTL1) registers
Table
UART Control registers must not be written while the UART is enabled.
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
to 0.
registers.
BRGCTL bit in the UART Control 1 register to 1.
UART Data Rate (bits/s)
Interrupt Interval s ( )
62) configure the properties of the UART’s transmit and receive operations. The
REN
R/W
6
0
CTSE
R/W
5
0
=
System Clock Period (s) BRG 15:0
=
-------------------------------------------------------------------------------- -
16
PEN
R/W
4
0
×
System Clock Frequency (Hz)
UART Baud Rate Divisor Value
F42H
PSEL
R/W
3
0
Universal Asynchronous Receiver/Transmitter
×
Z8 Encore! XP
SBRK
R/W
[
Infrared Encoder/Decoder
2
0
Product Specification
]
(Table 61
STOP
R/W
1
0
®
F082A Series
and
LBEN
R/W
0
0
on
108