Z8F042AHJ020SC00TR Zilog, Z8F042AHJ020SC00TR Datasheet - Page 71

• Manufacturer Part Number: Z8F042AHJ020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHJ020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHJ020SC00T

Table 33. Interrupt Request 0 Register (IRQ0)
Interrupt Control Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS022825-0908
Caution:
Interrupt Request 0 Register
Reserved
R/W
7
0
For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail
Trap, and the Watchdog Oscillator Fail Trap, the interrupt control registers enable
individual interrupts, set interrupt priorities, and indicate interrupt requests.
The Interrupt Request 0 (IRQ0) register
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 register to determine if any interrupt requests are pending.
Reserved—Must be 0.
T1I—Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
T0I—Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
To avoid re-triggerings of the Watchdog Timer interrupt after exiting the associated
interrupt service routine, it is recommended that the service routine continues to read
from the RSTSTAT register until the WDT bit is cleared as given in the following coding
sample:
CLEARWDT:
LDX r0, RSTSTAT
BTJNZ 5, r0, CLEARWDT
R/W
T1I
6
0
R/W
T0I
5
0
; read reset status register to clear wdt bit
U0RXI
R/W
4
0
; loop until bit is cleared
FC0H
(Table
U0TXI
R/W
33) stores the interrupt requests for both
3
0
Z8 Encore! XP
Reserved Reserved
R/W
2
0
Product Specification
R/W
1
0
®
Interrupt Controller
F082A Series
ADCI
R/W
0
0
60