HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 182

• Manufacturer Part Number: HD64F2134FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2134FA20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.5.3
Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts
by means of the I and UI bits in the CPU’s CCR, and ICR.
For example, if the interrupt enable bit for an interrupt request is set to 1, and H'20, H'00, and H'00
are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control
level 1 and other interrupts to control level 0), the situation is as follows:
Figure 5.9 shows the state transitions in these cases.
Rev. 4.00 Jun 06, 2006 page 126 of 1004
REJ09B0301-0400
Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when
set to 1.
Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and
disabled when both the I bit and the UI bit are set to 1.
When I = 0, all interrupts are enabled
(Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...)
When I = 1 and UI = 0, only NMI, IRQ2, IRQ3, and address break interrupts are enabled
When I = 1 and UI = 1, only NMI and address break interrupts are enabled
Exception handling execution
All interrupts enabled
Interrupt Control Mode 1
or I 1, UI 1
Figure 5.9 Example of State Transitions in Interrupt Control Mode 1
I 0
break interrupts enabled
Only NMI and address
I 1, UI 0
I 0
UI 0
Exception handling execution
and address break interrupts
Only NMI, IRQ2, IRQ3,
or UI 1
enabled