HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 588

• Manufacturer Part Number: HD64F2134FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2134FA20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 17 Host Interface [H8S/2138 Group]
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to
0 when the host processor reads ODR1.
Bit 0
OBF
0
1
Table 17.3 shows the conditions for setting and clearing the STR1 flags.
Table 17.3 Set/Clear Timing for STR1 Flags
Flag
C/D
IBF *
OBF
Note:
17.2.7
IDR2 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the
host processor. When CS2 is low, information on the host data bus is written into IDR2 at the
rising edge of IOW. The HA0 state is also latched into the C/D bit in STR2 to indicate whether the
written information is a command or data.
The initial values of IDR2 after a reset and in standby mode are undetermined.
Rev. 4.00 Jun 06, 2006 page 532 of 1004
REJ09B0301-0400
Bit
Initial value
Slave Read/Write
Host Read/Write
* The IBF flag setting and clearing conditions are different when the fast A20 gate is
Input Data Register 2 (IDR2)
used. For details see table 17.8, Fast A20 Gate Output Signals.
Description
[Clearing condition]
When the host processor reads ODR1 or the slave writes 0 in the OBF bit
[Setting condition]
When the slave processor writes to ODR1
Setting Condition
Rising edge of host’s write signal
(IOW) when HA0 is high
Rising edge of host’s write signal
(IOW) when writing to IDR1
Falling edge of slave’s internal write
signal (WR) when writing to ODR1
IDR7
—
W
R
7
IDR6
—
W
R
6
IDR5
—
W
R
5
IDR4
—
W
R
4
Clearing Condition
Rising edge of host’s write signal (IOW) when
HA0 is low
Falling edge of slave’s internal read signal
(RD) when reading IDR1
Rising edge of host’s read signal (IOR) when
reading ODR1
IDR3
—
W
R
3
IDR2
—
W
R
2
IDR1
—
W
R
1
(Initial value)
IDR0
—
W
R
0