HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 30

• Manufacturer Part Number: HD64F2134FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2134FA20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.3 Operation .......................................................................................................................... 536
17.4 Interrupts ........................................................................................................................... 541
17.5 Usage Note........................................................................................................................ 542
Section 18 D/A Converter
18.1 Overview........................................................................................................................... 543
18.2 Register Descriptions ........................................................................................................ 546
18.3 Operation .......................................................................................................................... 549
Section 19 A/D Converter
19.1 Overview........................................................................................................................... 551
19.2 Register Descriptions ........................................................................................................ 555
19.3 Interface to Bus Master ..................................................................................................... 561
19.4 Operation .......................................................................................................................... 562
Rev. 4.00 Jun 06, 2006 page xxviii of liv
17.2.9 Status Register 2 (STR2) ..................................................................................... 533
17.2.10 Module Stop Control Register (MSTPCR) .......................................................... 535
17.3.1 Host Interface Operation...................................................................................... 536
17.3.2 Control States....................................................................................................... 536
17.3.3 A20 Gate .............................................................................................................. 537
17.3.4 Host Interface Pin Shutdown Function ................................................................ 539
17.4.1 IBF1, IBF2 ........................................................................................................... 541
17.4.2 HIRQ11, HIRQ1, and HIRQ12............................................................................ 541
18.1.1 Features................................................................................................................ 543
18.1.2 Block Diagram ..................................................................................................... 544
18.1.3 Input and Output Pins .......................................................................................... 545
18.1.4 Register Configuration......................................................................................... 545
18.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 546
18.2.2 D/A Control Register (DACR) ............................................................................ 546
18.2.3 Module Stop Control Register (MSTPCR) .......................................................... 548
19.1.1 Features................................................................................................................ 551
19.1.2 Block Diagram ..................................................................................................... 552
19.1.3 Pin Configuration................................................................................................. 553
19.1.4 Register Configuration......................................................................................... 554
19.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 555
19.2.2 A/D Control/Status Register (ADCSR) ............................................................... 556
19.2.3 A/D Control Register (ADCR) ............................................................................ 558
19.2.4 Keyboard Comparator Control Register (KBCOMP) .......................................... 559
19.2.5 Module Stop Control Register (MSTPCR) .......................................................... 560
19.4.1 Single Mode (SCAN = 0) .................................................................................... 562
19.4.2 Scan Mode (SCAN = 1)....................................................................................... 564
19.4.3 Input Sampling and A/D Conversion Time ......................................................... 565
................................................................................................. 543
................................................................................................. 551