HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 211

no-image

HD64F2134FA20

Manufacturer Part Number
HD64F2134FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of HD64F2134FA20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2134FA20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F2134FA20V
Manufacturer:
RENESAS
Quantity:
201
6.5.3
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait
Control.
Wait states cannot be inserted in a burst cycle.
6.6
6.6.1
When the H8S/2138 Group or H8S/2134 Group chip accesses external space, it can insert a 1-state
idle cycle (T
inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a
long output floating time, and high-speed memory, I/O interfaces, and so on.
If an external write occurs after an external read while the ICIS0 bit in BCR is set to 1, an idle
cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal
mode.
Figure 6.9 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Idle Cycle
Operation
Wait Control
I
) between bus cycles when a write cycle occurs immediately after a read cycle. By
Rev. 4.00 Jun 06, 2006 page 155 of 1004
Section 6 Bus Controller
REJ09B0301-0400

Related parts for HD64F2134FA20