HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 611

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HD64F2134FA20

Manufacturer Part Number
HD64F2134FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of HD64F2134FA20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2134FA20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F2134FA20V
Manufacturer:
RENESAS
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201
19.2
19.2.1
Bit
Initial value
Read/Write
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion.
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in table
19.3.
The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for
the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section
19.3, Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode, watch mode,
subactive mode, subsleep mode, and module stop mode.
Table 19.3 Analog Input Channels and Corresponding ADDR Registers
Group 0
AN0
AN1
AN2
AN3
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
Analog Input Channel
AD9
15
R
0
AD8
14
R
0
Group 1
AN4
AN5
AN6 or CIN0 to CIN7
AN7
AD7
13
R
0
AD6
12
R
0
AD5
11
R
0
AD4
10
R
0
AD3
R
9
0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
AD2
R
8
0
Rev. 4.00 Jun 06, 2006 page 555 of 1004
AD1
R
7
0
AD0
R
6
0
R
5
0
Section 19 A/D Converter
R
4
0
R
3
0
REJ09B0301-0400
R
2
0
R
1
0
R
0
0

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