M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 164

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.4
6.5.4.1 Address Registers (I2CADDR)
6.5.4.2 Data Register (I2CDAT)
The CPU interfaces to the SIO port through the following thirteen special function registers:
I2CON (control register), I2CSTATUS (status register), I2CDAT (data register), I2CADDRn
(address registers, n=0~3), I2CADMn (address mask registers, n=0~3), I2CLK (clock rate
register) and I2CTOC (Time-out counter register). All bit 31~ bit 8 of these I2C special function
registers are reserved. These bits do not have any functions and are all zero if read back.
When I2C port is enabled by setting ENS1 (I2CON [6]) to high, the internal states will be
controlled by I2CON and I2C logic hardware. Once a new status code is generated and stored in
I2CSTATUS, the I2C Interrupt Flag bit SI (I2CON [3]) will be set automatically. If the Enable
Interrupt bit EI (I2CON [7]) is set high at this time, the I2C interrupt will be generated. The bit field
I2CSTATUS[7:3] stores the internal state code, the lowest 3 bits of I2CSTATUS are always zero
and the content keeps stable until SI is cleared by software. The base address of I2C is
4002_0000.
I2C port is equipped with four slave address registers I2CADDRn (n=0~3). The contents of the
register are irrelevant when I2C is in master mode. In the slave mode, the bit field I2CADDRn[7:1]
must be loaded with the MCU’s own slave address. The I2C hardware will react if the contents of
I2CADDR are matched with the received slave address.
The I2C ports support the “General Call” function. If the GC bit (I2CADDRn [0]) is set the I2C port
hardware will respond to General Call address (00H). Clear GC bit to disable general call
function.
When GC bit is set and the I2C is in Slave mode, it can receive the general call address by 00H
after Master send general call address to I2C bus, then it will follow status of GC mode.
I2C-bus controllers support multiple address recognition with four address mask registers
I2CADMn (n=0~3). When the bit in the address mask register is set to one, it means the received
corresponding address bit is don’t-care. If the bit is set to zero, that means the received
corresponding register bit should be exact the same as address register.
This register contains a byte of serial data to be transmitted or a byte which just has been
received. The CPU can read from or write to this 8-bit (I2CDAT [7:0]) directly while it is not in the
process of shifting a byte. When I2C is in a defined state and the serial interrupt flag (SI) is set.
Data in I2CDAT [7:0] remains stable as long as SI bit is set. While data is being shifted out, data
on the bus is simultaneously being shifted in; I2CDAT [7:0] always contains the last data byte
present on the bus. Thus, in the event of arbitration lost, the transition from master transmitter to
slave receiver is made with the correct data in I2CDAT [7:0].
I2CDAT [7:0] and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled
I2C Protocol Registers
NuMicro M051
™
Series Technical Reference Manual
- 164 -
Publication Release Date: Sep 14, 2010
Revision V1.2