M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 337

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

™
NuMicro M051
Series Technical Reference Manual
Figure 6.12-3 Connection of 8-bit EBI Data Width with 8-bit Device
When system access data width is larger than EBI data width, EBI controller will finish a system
access command by operating EBI access more than once. For example, if system requests a
32-bit data through EBI device, EBI controller will operate accessing four times when setting EBI
data width with 8-bit.
6.12.4.3 EBI Operating Control
MCLK Control
™
In NuMicro M051
series, all EBI signals will be synchronized by MCLK when EBI is operating.
™
When NuMicro M051
series connects to the external device with slower operating frequency,
the MCLK can divide most to HCLK/32 by setting MCLKDIV of register EBICON. Therefore,
™
NuMicro M051
can suitable for a wide frequency range of EBI device. If MCLK is set to HCLK/1,
EBI signals are synchronized by positive edge of MCLK, else by negative edge of MCLK.
Operation and Access Timing Control
In the start of access, chip select (nCS) asserts to low and wait one MCLK for address setup time
(tASU) for address stable. Then ALE asserts to high after address is stable and keeps for a period
of time (tALE) for address latch. After latch address, ALE asserts to low and wait one MCLK for
latch hold time (tLHD) and another one MCLK cycle (tA2D) that is inserted behind address hold
time to be the bus turn-around time for address change to data. Then nRD asserts to low when
read access or nWR asserts to low when write access. Then nRD or nWR asserts to high after
keeps access time (tACC) for reading output stable or writing finish. After that, EBI signals keep
Publication Release Date: Sept 14, 2010
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Revision V1.2