M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 166

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.4.4 Status Register (I2CSTATUS)
6.5.4.5 I2C Clock Baud Rate Bits (I2CLK)
6.5.4.6 The I2C Time-out Counter Register (I2CTOC)
I2CSTATUS [7:0] is an 8-bit read-only register. The three least significant bits are always 0. The
bit field I2CSTATUS [7:3] contain the status code. There are 26 possible status codes, All states
are listed in section 6.5.6. When I2CSTATUS [7:0] contains F8H, no serial interrupt is requested.
All other I2CSTATUS [7:3] values correspond to defined SIO states. When each of these states is
entered, a status interrupt is requested (SI = 1). A valid status code is present in I2CSTATUS[7:3]
one cycle after SI is set by hardware and is still present one cycle after SI has been reset by
software.
In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP
condition is present at an illegal position in the format frame. Examples of illegal positions are
during the serial transfer of an address byte, a data byte or an acknowledge bit. To recover I2C
from bus error, STO should be set and SI should be clear to enter not addressed slave mode.
Then clear STO to release bus and to wait new communication. I2C bus can not recognize stop
condition during this action when bus error occurs.
The data baud rate of I2C is determines by I2CLK [7:0] register when SIO is in a master mode. It
is not important when SIO is in a slave mode. In the slave modes, SIO will automatically
synchronize with any clock frequency up to 1 MHz from master I2C device.
The data baud rate of I2C setting is Data Baud Rate of I2C = APBCLK / (4x (I2CLK [7:0] +1)). If
PCLK=16 MHz, the I2CLK [7:0] = 40 (28H), so data baud rate of I2C = 16 MHz/ (4x (40 +1)) =
97.5 Kbits/sec.
There is a 14-bit time-out counter which can be used to deal with the I2C bus hang-up. If the time-
out counter is enabled, the counter starts up counting until it overflows (TIF=1) and generates I2C
interrupt to CPU or stops counting by clearing ENTI to 0. When time-out counter is enabled,
setting flag SI to high will reset counter and re-start up counting after SI is cleared. If I2C bus
hangs up, it causes the I2CSTATUS and flag SI are not updated for a period, the 14-bit time-out
counter may overflow and acknowledge CPU the I2C interrupt. Refer to the Figure 6.5-9 for the
14-bit time-out counter. User can clear TIF by writing 1 to this bit.
NuMicro M051
™
Series Technical Reference Manual
- 166 -
Publication Release Date: Sep 14, 2010
Revision V1.2