M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 239

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7.5
NuMicro M051
In master/slave mode, the active level of device/slave select (SPISS) signal can be programmed
to low active or high active in SS_LVL bit (SPI_SSR [2]), but the SPISS0/1 is level trigger or edge
trigger which is defined in SS_LTRIG bit (SPI_SSR [4]). The serial clock (SPICLK) idle state can
be configured as high state or low state by setting the CLKP bit (SPI_CNTRL [11]). It also
provides the bit length of a transfer word in TX_BIT_LEN (SPI_CNTRL [7:3]), the transfer number
in TX_NUM (SPI_CNTRL [8]), and transmit/receive data from MSB or LSB first in LSB bit
(SPI_CNTRL [10]). Users also can select which edge of serial clock to transmit/receive data in
TX_NEG/RX_NEG (SPI_CNTRL [2:1]) registers. Four SPI timing diagrams for master/slave
operations and the related settings are shown from Figure 6.7-8 to Figure 6.7-11.
SPI Timing Diagram
™
Figure 6.7-8 SPI Timing in Master Mode
Series Technical Reference Manual
- 239 -
Publication Release Date: Sept 14, 2010
Revision V1.2