M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 247

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

NuMicro M051
[18]
[17]
[16]
[15:12]
[11]
[10]
SLAVE
IE
IF
SP_CYCLE
CLKP
LSB
™
Series Technical Reference Manual
configured as 0x00. (32 bits/word)
10 = Enable Byte Reorder function, but disable byte suspend function.
11 = Disable Byte Reorder function, but insert a suspend interval (2~17 serial
clock cycles) among each byte. The setting of TX_BIT_LEN must be configured
as 0x00. (32 bits/word)
Slave Mode Indication
0 = Master mode.
1 = Slave mode.
Interrupt Enable
0 = Disable SPI/MICROWIRE Interrupt.
1 = Enable SPI/MICROWIRE Interrupt.
Interrupt Flag
0 = It indicates that the transfer dose not finish yet.
1 = It indicates that the transfer is done. The interrupt flag is set if it was enable.
NOTE: This bit is cleared by writing 1 to itself.
Suspend Interval (Master Only)
These four bits provide configurable suspend interval between two successive
transmit/receive transaction in a transfer. The suspend interval is from the last
falling clock edge of the current transaction to the first rising clock edge of the
successive transaction if CLKP = 0. If CLKP = 1, the interval is from the rising
clock edge to the falling clock edge. The default value is 0x0. When TX_NUM =
00b, setting this field has no effect on transfer. The desired suspend interval is
obtained according to the following equation:
(SP_CYCLE[3:0] + 2) * period of SPICLK
SP_CYCLE = 0x0 … 2 SPICLK clock cycle
SP_CYCLE = 0x1 … 3 SPICLK clock cycle
……
SP_CYCLE = 0xe … 16 SPICLK clock cycle
SP_CYCLE = 0xf … 17 SPICLK clock cycle
Clock Polarity
0 = SPICLK idle low.
1 = SPICLK idle high.
LSB First
0 = The MSB is transmitted/received first (which bit in SPI_TX0/1 and
SPI_RX0/1 register that is depends on the TX_BIT_LEN field).
1 = The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit
received from the line will be put in the LSB position in the RX register (bit 0 of
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Publication Release Date: Sept 14, 2010
Revision V1.2