M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 352

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Several error conditions are checked after s/w writes ISPGO bit. If error condition occurs, ISP
operation is not been started and ISP fail flag will be set instead of. ISPFF flag is cleared by s/w, it
will not be over written in next ISP operation. The next ISP procedure can be started even ISPFF
bit keeps at 1. It is recommended that software to check ISPFF bit and clear it after each ISP
operation if it is set to 1.
When ISPGO bit is set, CPU will wait for ISP operation finish, during this period; peripheral still
keeps working as usual. If any interrupt request occur, CPU will not service it till ISP operation
finish.
Note that NuMicro M051™ series allows user to update CONFIG value by ISP, but for application
program code security issue, software is required to erase APROM by page erase before erase
CONFIG. Otherwise, erase CONFIG will not be allowed.
HREADY
HCLK
NuMicro M051
CPU writes ISPGO bit
Figure 6.13-6 ISPGo Timing Diagram
™
Series Technical Reference Manual
CPU is halted but other peripherials keep working
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ISP operation
Publication Release Date: Sep 14, 2010
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Revision V1.2