M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 297

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

FIFO Status Register (UA_FSR)
NuMicro M051
Register
UA_FSR
Bits
[31:29]
[28]
[27:24]
[23]
[22]
[21:16]
RX_OVERL
TX_OVER
Reserved
31
23
15
7
Offset
UART0_BA+0x18
UART1_BA+0x18
Descriptions
Reserved
TE_FLAG
Reserved
TX_OVER
TX_EMPTY
TX_POINTER
RX_EMPTY
TX_EMPTY
Reserved
BIF
30
22
14
6
™
Reserved
Transmitter Empty Flag (Read Only)
Bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the
last byte has been transmitted.
Bit is cleared automatically when TX FIFO is not empty or the last byte transmission
has not completed.
Reserved
Transmitter FIFO Over (Read Only)
This bit indicates TX FIFO overflowing or not.
If the number of bytes of transmitting data is greater than TX_FIFO (UA_RBR) size,
15 bytes of UART0/UART1, this bit will be set. Otherwise is cleared by hardware.
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
When the last byte of TX FIFO has been transferred to Transmitter Shift Register,
hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not
empty).
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into
FEF
R/W
R/W
R/W
29
21
13
5
Series Technical Reference Manual
Description
UART0 FIFO Status Register
UART1 FIFO Status Register
TE_FLAG
PEF
28
20
12
4
- 297 -
485_ADD_D
ETF
RS-
27
19
11
3
RX_POINTER
TX_POINTER
Publication Release Date: Sept 14, 2010
26
18
10
2
Reserved
Reserved
25
17
9
1
Revision V1.2
0x1040_4000
0x1040_4000
Reset Value
24
16
8
0