S29GL256P11TFI010 Spansion Inc., S29GL256P11TFI010 Datasheet - Page 37

• Manufacturer Part Number: S29GL256P11TFI010
• Description: Flash 3V 256Mb Mirrorbit highest address110ns
• Manufacturer: Spansion Inc.

Specifications of S29GL256P11TFI010

• Memory Type: NOR
• Memory Size: 256 Mbit
• Access Time: 110 ns
• Data Bus Width: 8 bit, 16 bit
• Architecture: Uniform
• Interface Type: Page-mode
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 50 mA
• Mounting Style: SMD/SMT
• Operating Temperature: + 85 C
• Package / Case: TSOP-56
• Memory Configuration: 128K X 16
• Ic Interface Type: Parallel
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.9
November 21, 2006 S29GL-P_00_A3
7.9.1
7.9.2
Writing Commands/Command Sequences
RY/BY#
Hardware Reset
Notes
1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation
During a write operation, the system must drive CE# and WE# to V
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is
latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or
the entire device.
address space is divided into uniform 64KW/128KB sectors. A sector address is the set of address bits
required to uniquely select a sector. I
the write mode. “AC Characteristics” contains timing specification tables and timing diagrams for write
operations.
This feature allows the host system to detect when data is ready to be read by simply monitoring the RY/BY#
pin, which is a dedicated output and controlled by CE#.
The device address space is divided into uniform 64KW/128KB sectors. A sector address is the set of
address bits required to uniquely select a sector.
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t
all outputs, resets the configuration register, and ignores all read/write commands for the duration of the
RESET# pulse. The device also resets the internal state machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence.
When RESET# is held at V
V
system to read the boot-up firmware from the Flash memory upon a system reset. See
on page 53
SS
Standard
Suspend
Suspend
Program
Write-to-
Refer to the section on DQ5 for more information.
Erase
Buffer
Mode
Mode
Mode
D a t a
, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the
and
Program-
Suspend
Suspend
S h e e t
Embedded Program Algorithm
Erase-
Read
Read
Embedded Erase Algorithm
Erase-Suspend-Program
Figure 11.8 on page 54
(Embedded Program)
Table 6.2–Table 6.3
Status
Abort
Busy
Program-Suspended
Suspended Sector
Suspended Sector
Erase-Suspended
( A d v a n c e
(Note 3)
(Note 4)
Non-Program
SS
Non-Erase
S29GL-P MirrorBit
, the device draws V
Sector
Sector
RP
CC2
Table 7.17 Write Operation Status
, the device immediately terminates any operation in progress, tristates
indicate the address space that each sector occupies. The device
in “DC Characteristics” represents the active current specification for
for timing diagrams.
(Note 2)
I n f o r m a t i o n )
DQ7#
DQ7#
DQ7#
DQ7#
DQ7
TM
0
1
Flash Family
CC
reset current (I
No toggle
Toggle
Toggle
Toggle
Toggle
Toggle
DQ6
Invalid (not allowed)
(Note 1)
DQ5
IL
CC5
0
0
0
0
0
0
and OE# to V
Data
Data
). If RESET# is held at V
DQ3
N/A
N/A
N/A
N/A
N/A
1
No toggle
IH
(Note 2)
Toggle
Toggle
DQ2
when providing an
N/A
N/A
N/A
Figure 11.7
DQ1
N/A
N/A
N/A
IL
0
0
1
, but not at
BY#
RY/
0
0
1
1
1
1
0
0
0
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