LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 101

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3-18. Configuration from PROGRAMN Timing
Figure 3-19. Wake-Up Timing
Figure 3-20. SPI/SPIm Configuration Waveforms
PROGRAMN
CSSPI[0:1]N
SISPI/BUSY
D7/SPID0
DONE
CCLK
INITN
VCC
DPPDONE
t
PROGRAMN
PROGRAMN
DPPINIT
USER I/O
USER I/O
t
CFG[2:0]
1. The CFG pins are normally static (hard wired)
PRGM
t
ICFG
DONE
DONE
INITN
CCLK
INITN
CCLK
t
DINIT
t
Capture
DPPINIT
t
t
CFGx
DINITD
CFGX
t
CSSPI
Wake-Up
t
CSCCLK
OPCODE
Capture
t
SOE
t
CSPID
t
IOENSS
t
IODISS
D7
0
t
SOCDO
1
D6
t
PRGM
2
D5 D4 D3 D2 D1 D0
3-49
3
4
5
t
MWC
6
t
DINIT
7
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Clock 127
t
XXX
SUCFG
0
Clock 128
Valid
Valid Bitstream
t
HCFG