LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 385

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
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September 2006
For Further Information
A variety of technical notes for the LatticeECP2/M family are available on the Lattice web site at www.latticesemi.com.
For further information about interface standards refer to the following web sites:
• TN1124,
• TN1102,
• TN1103,
• TN1104,
• TN1105,
• TN1106,
• TN1107,
• TN1108,
• TN1109,
• TN1113,
• TN1162,
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• PCI: www.pcisig.com
LatticeECP2M SERDES/PCS Usage Guide
LatticeECP2/M sysIO Usage Guide
LatticeECP2/M sysCLOCK PLL Design and Usage Guide
LatticeECP2/M Memory Usage Guide
LatticeECP2/M High-Speed I/O Interface
Power Estimation and Management for LatticeECP2/M Devices
LatticeECP2/M sysDSP Usage Guide
LatticeECP2/M sysCONFIG Usage Guide
LatticeECP2/M Configuration Encryption Usage Guide
LatticeECP2/M Soft Error Detection (SED) Usage Guide
LatticeECP2/M Hardware Checklist
LatticeECP2/M Family Data Sheet
6-1
Supplemental Information
DS1006
Data Sheet DS1006
Further Info_01.0