LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 23
LFE2M35E-6FN484C
Manufacturer Part Number
LFE2M35E-6FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
Manufacturer
Lattice
Series
LatticeECP2Mr
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M35E-6FN484C
Number Of Macrocells
34000
Maximum Operating Frequency
357 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
No. Of Logic Blocks
34000
No. Of Macrocells
16000
No. Of Speed Grades
6
Total Ram Bits
2101Kbit
No. Of I/o's
303
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associ-
ated resets for both ports are as shown in Figure 2-20.
Figure 2-20. Memory Core Reset
For further information about the sysMEM EBR block, please see the the list of additional technical documentation
at the end of this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-21. The GSR input to the
EBR is always asynchronous.
Figure 2-21. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
mode is supported for all data widths.
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-20
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeECP2/M Family Data Sheet
Port A[17:0]
Port B[17:0]
MAX
(EBR clock). The reset
Architecture
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