LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 319

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)
Lattice Semiconductor
Ball Number
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
M30
M29
R23
R22
R29
N30
N29
R27
R28
R26
N22
N24
N23
N25
N26
T22
T29
T28
P30
T27
T26
P29
P28
P23
P24
P27
P25
P26
K30
K29
P22
J30
J29
-
Ball/Pad Function
GNDIO3
GNDIO3
GNDIO2
GNDIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO2
VCCIO2
PR69A
PR68B
PR68A
PR64B
PR64A
PR59A
PR57B
PR57A
PR55A
PR53B
PR53A
PR51B
PR66B
PR66A
PR65B
PR65A
PR61B
PR61A
PR60B
PR60A
PR59B
PR56B
PR56A
PR55B
PR54B
PR54A
PR52B
PR52A
PR51A
PR50B
PR50A
PR48B
PR48A
-
LFE2M100E/SE
Bank
4-216
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
-
-
-
RUM3_SPLLC_FB_A/RDQ54
RLM4_SPLLC_FB_A/RDQ63
RUM3_SPLLT_FB_A/RDQ54
RUM3_SPLLC_IN_A/RDQ54
RLM4_SPLLT_FB_A/RDQ63
RLM4_SPLLC_IN_A/RDQ63
RUM3_SPLLT_IN_A/RDQ54
RLM4_SPLLT_IN_A/RDQ63
PCLKC3_0/RDQ63
PCLKC2_0/RDQ54
LatticeECP2/M Family Data Sheet
PCLKT3_0/RDQ63
PCLKT2_0/RDQ54
VREF2_3/RDQ63
VREF1_3/RDQ63
Dual Function
RDQS54
RDQ72
RDQ72
RDQ72
RDQ63
RDQ63
RDQ63
RDQ63
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
RDQ45
RDQ45
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T