LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 48

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-14. Supported Output Standards
Hot Socketing
LatticeECP2/M devices have been carefully designed to ensure predictable behavior during power-up and power-
down. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is
high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. This
allows for easy integration with the rest of the system. These capabilities make the LatticeECP2/M ideal for many
multiple power supply and hot-swap applications.
Single-ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
HSTL18 Class I, II
HSTL15 Class I
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I, II
Differential Interfaces
Differential SSTL3, Class I, II
Differential SSTL2, Class I, II
Differential SSTL18, Class I, II
Differential HSTL18, Class I, II
Differential HSTL15, Class I
LVDS
MLVDS
BLVDS
LVPECL
RSDS
LVCMOS33D
1. Emulated with external resistors. For more detail, please see information regarding additional technical documentation at
the end of this data sheet.
1
1
1
1
Output Standard
1
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA, 16mA
4mA, 8mA, 12mA 16mA
4mA, 8mA
2mA, 6mA
4mA, 8mA
2mA, 6mA
2-45
Drive
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LatticeECP2/M Family Data Sheet
V
CCIO
3.3
3.3
2.5
1.5
1.2
3.3
1.8
1.5
3.3
2.5
3.3
2.5
1.8
1.8
1.5
2.5
2.5
2.5
3.3
2.5
3.3
1.8
—
—
—
—
—
1.8
(Nom.)
Architecture