LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 33

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-28. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-28.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
DDRCLKPOL*
*Signals are available on left/right/bottom edges only.
** Selected blocks.
DQSXFER*
QNEG0*
QNEG1*
ONEG2*
QPOS0*
QPOS1*
OPOS2*
ONEG0
OPOS0
ONEG1
INDD
OPOS1
INCK**
ECLK1
ECLK2
IPOS0
IPOS1
GSRN
INFF
CLK
LSR
CE
TD
Control
Muxes
CLK1
CLK0
CEO
GSR
LSR
CEI
2-30
PIOA
Register
Register
Register
Tristate
Output
Block
Block
Block
Input
PIOB
IOLD0
IOLT0
DI
LatticeECP2/M Family Data Sheet
Buffer
sysIO
PADB
PADA
“C”
“T”
Architecture