LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 37

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges
DQSXFER
DQSXFER
ONEG1
ONEG0
ONEG1
ONEG0
OPOS1
OPOS0
OPOS1
OPOS0
(CLKA)
(CLKB)
ECLK1
ECLK2
ECLK1
ECLK2
CLKA
CLKB
CLK1
CLK1
TD
TD
* Shared with input register
Clock Transfer
Clock Transfer
Registers
Registers
D
D
D-Type*
D-Type*
D-Type
D-Type
D
D
Tristate Logic
Tristate Logic
Q
Q
Q
Q
*
*
D
D
Latch
Latch
Q
Q
0
1
0
1
0
1
0
1
2-34
Note: Simplified version does not show CE and SET/RESET details
0
1
0
1
0
1
0
1
D
D
D
D
D
D
D
D
/LATCH
/LATCH
/LATCH
/LATCH
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
LatticeECP2/M Family Data Sheet
Q
Q
Q
Q
Q
Q
Q
Q
Comp PIO (B) in LVDS I/O Pair
True PIO (A) in LVDS I/O Pair
D
D
D
D
DDR Output
DDR Output
Latch
Latch
Latch
Latch
Registers
Registers
Q
Q
Q
Q
Output Logic
Output Logic
0
1
0
1
0
1
0
1
0
1
0
1
Programmable
Programmable
Control
Control
0
1
0
1
Architecture
0
1
0
1
DO
DO
TO
TO