LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 310

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)
Lattice Semiconductor
Ball Number
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
H1
N9
N7
M6
M5
N5
N6
M4
M3
M2
R5
R4
M1
N2
R8
N1
K2
K1
P9
P7
P6
P8
P5
P4
T9
P3
P2
P1
T5
T4
J2
J1
L5
L4
L3
L2
L1
Ball/Pad Function
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO7
PL34B
PL35A
PL35B
PL41A
PL41B
PL42A
PL42B
PL43A
PL43B
PL44A
PL44B
PL45A
PL45B
PL46A
PL46B
PL47A
PL47B
PL48A
PL48B
PL50A
PL50B
PL51A
PL51B
PL52A
PL52B
PL53A
PL53B
PL54A
PL54B
PL55A
PL55B
PL56A
PL56B
PL57A
PL57B
PL59A
PL59B
LFE2M100E/SE
Bank
4-207
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
-
-
-
-
-
-
LUM3_SPLLC_FB_A/LDQ54
LUM3_SPLLT_FB_A/LDQ54
LUM3_SPLLC_IN_A/LDQ54
LUM3_SPLLT_IN_A/LDQ54
LatticeECP2/M Family Data Sheet
PCLKC7_0/LDQ54
PCLKC6_0/LDQ63
PCLKT7_0/LDQ54
PCLKT6_0/LDQ63
Dual Function
LDQS45
LDQS54
LDQ32
LDQ32
LDQ32
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ45
LDQ54
LDQ54
LDQ54
LDQ54
LDQ54
LDQ54
LDQ54
LDQ54
LDQ54
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T