LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 255

FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd

LFE2M35E-6FN484C

Manufacturer Part Number
LFE2M35E-6FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
Manufacturer
Lattice
Series
LatticeECP2Mr
Datasheet

Specifications of LFE2M35E-6FN484C

Number Of Macrocells
34000
Maximum Operating Frequency
357 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
No. Of Logic Blocks
34000
No. Of Macrocells
16000
No. Of Speed Grades
6
Total Ram Bits
2101Kbit
No. Of I/o's
303
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFE2M35E-6FN484C
Manufacturer:
Lattice
Quantity:
135
Part Number:
LFE2M35E-6FN484C
Manufacturer:
LATTICE
Quantity:
168
Part Number:
LFE2M35E-6FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFE2M35E-6FN484C-5I
Manufacturer:
LATTICE
Quantity:
1
Lattice Semiconductor
LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA
Number
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
***For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices
(ECP2M20 and ECP2M35). They can be either sysCONFIG pins or general purpose I/Os. These pins are dedicated sysCONFIG pins for the
higher density devices (ECP2M50, ECP2M70 and ECP2M100).
****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
M10
M11
M12
M13
W16
W21
Ball
N10
N11
N12
N13
N15
N20
P14
R10
R13
Y10
Y13
D15
G14
G15
D14
E15
E14
G12
G13
L10
L11
L12
L13
T19
F15
F14
F13
W2
W7
N3
N8
K3
K8
P9
T4
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Bank
LFE2M20E/SE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Dual Function
Differential
4-152
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LatticeECP2/M Family Data Sheet
Bank
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LFE2M35E/SE
Dual Function
Pinout Information
Differential

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